(Hong Kong)
Product Summary
The GAL16V8B-25QP is a high performance ECMOS PLD generic array logic. At 5ns maximum propagation delay time, it combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the GAL16V8B-25QP to be reprogrammed quickly and efficiently.
Parametrics
GAL16V8B-25QP absolute maxing ratings: (1)Supply voltage VCC: –0.5 to +7V; (2)Input voltage applied: –2.5 to VCC +1.0V; (3)Off-state output voltage applied: –2.5 to VCC +1.0V; (4)Storage Temperature: –65 to 150℃; (5)Ambient Temperature with Power Applied: –55 to 125℃.
Features
GAL16V8B-25QP features: (1)HIGH PERFORMANCE ECMOS TECHNOLOGY: 5 ns Maximum Propagation Delay; Fmax = 166 MHz; 4 ns Maximum from Clock Input to Data Output; UltraMOS Advanced CMOS Technology; (2)50% to 75% REDUCTION IN POWER FROM BIPOLAR: 75mA Typ Icc on Low Power Device; 45mA Typ Icc on Quarter Power Device; (3)ACTIVE PULL-UPS ON ALL PINS; (4)E CELL TECHNOLOGY: Reconfigurable Logic; Reprogrammable Cells; 100% Tested/Guaranteed 100% Yields; High Speed Electrical Erasure (<100ms); 20 Year Data Retention.
Diagrams
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 GAL16LV8 |
Other |
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Data Sheet |
Negotiable |
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GAL16LV8C-10LJ |
Lattice |
SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD |
Data Sheet |
Negotiable |
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GAL16LV8C-10LJN |
Lattice |
SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD |
Data Sheet |
Negotiable |
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GAL16LV8C-15LJ |
Lattice |
SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD |
Data Sheet |
Negotiable |
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GAL16LV8C-15LJN |
Lattice |
SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD |
Data Sheet |
Negotiable |
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GAL16LV8C-7LJ |
Lattice |
SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD |
Data Sheet |
Negotiable |
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